This application claims the priority of Korean Patent Application No. 10-2004-0072470, filed on Sep. 10, 2004, in the Korean Intellectual Property Office. The entire content of Korean Patent Application No. 10-2004-0072470, filed on Sep. 10, 2004 is hereby incorporated herein by reference.
1. Field
The present application relates to electronic circuitry and more particularly to level shifting circuitry.
2. Background Discussion
Level shifting circuitry is commonly used in semiconductor integrated circuits to transfer signals between two logic circuits having different operating voltages. FIG. 1 is a circuit diagram of a simple level shifting circuit 120 that changes the signal level between logic circuit 110 and logic circuit 130. Logic circuits 110 and 130 have different operating voltages. Referring to FIG. 1, the first logic circuit 110 operates at a voltage levels VCC and VSS1. Level VCC is a logic high level and level VSS1 is a logic low level. The second logic circuit 130 operates at voltage levels VCC and VSS2. In circuit 130, voltage level VCC is a logic high level and voltage level VSS2 is a logic low level. The level shifting circuit 120 receives an output signal from the first logic circuit 110, changes the level of the received signal, and transfers the changed signal to the second logic circuit 130. The logic high voltage level of logic circuits 110 and 130 is VCC and the logic low levels of logic circuits 110 and 130 are VSS1 and VSS2, respectively.
The level shifting circuit 120 operates as an inverter. Circuit 120 includes a P-type metal-oxide-semiconductor field effect transistor (MOSFET) P1, and an N-type MOSFET N1. The level shifting circuit 120 changes the level of the signal output from the first logic circuit 110 from VCC to VSS2, or from VSS1 to VCC and sends the changed signals to the second logic circuit 130.
When the level of a signal input to the level shifting circuit 120 is VSS1, the voltage VSS1 is applied to a gate terminal of the N-type MOSFET N1, and the voltage between the gate and source of the N-type MOSFET N1 is VSS1-VSS2. When VSS1-VSS2 is less than a threshold voltage of the N-type MOSFET N1, the N-type MOSFET N1 is not turned on. However, leakages occur due to a sub-threshold current in the N-type MOSFET N1, and hence power may be wasted. Such leakage current can be reduced to a few amps or less by implanting ions into a channel of the N-type MOSFET N1 to raise the threshold voltage. However, in order to implant ions into a channel, an additional ion-implanting process step is necessary. Further, an additional mask is required for the ion-implanting process. Thus, the cost of production is increased. Also, it is difficult to optimize a design for controlling the threshold voltage of the N-type MOSFET N1. Finally, the reliability of such circuitry is not particularly high.
Leakage current can be reduced by using the level shifting circuit 220 shown in FIG. 2. Circuit 220 changes signal level between two logic circuits 210 and 220 that have different operating voltages.
The level shifting circuit 220 shown in FIG. 2 changes the level of the signal output from the first logic circuit 210 from VCC to VSS2 and from VSS1 to VCC. The level shifting circuit 220 has a cross-coupled latch structure including P-type MOSFETs P2 and P3 and N-type MOSFETs N2 and N3.
When the level of the signal applied to the gate of the P-type MOSFET P2 is VSS1, the N-type MOSFET N3 is turned on and the voltage level VSS2 is applied to a gate terminal of the N-type MOSFET N2. In like manner, when the level of the signal at the input P-type MOSFET P3 is VSS1, the voltage level VSS2 is applied to a gate terminal of the N-type MOSFET N3.
In the level shifting circuit 220, the voltage between the gate and source of each of the N-type MOSFETs N2 and N3 is constant at zero volts, and therefore the leakage current is reduced. However, since the voltage is applied to the gate of the N-type MOSFET N2 or N3 through the P-type MOSFET P2 or P3, during the time period in which the voltage of the gate of the N-type MOSFET N2 or N3 goes from VCC to VSS2, a transient current may flow between the P-type MOSFETs P2 and P3 and in the N-type MOSFETs N2 and N3. The larger the difference between VSS1 and VSS2, the larger the transient current.